In many data communication arrangements, separate clock signals are not transmitted with the data. This requires recovering the clock from the data at the receiving end in order to then recover the data itself. With rapidly developing processor technology, demands for high-speed input/output (I/O) communication arrangements are ever increasing.
However, with high-speed input/output (I/O) communication arrangements, design challenges and complexity of the I/O receiver increase significantly. Not only does the receiver have to operate at higher data rates, but also the receiver sensitivity has to be improved as well due to the shorter time length of a received signal.
One type of receiver topology has been demonstrated, and often is considered ‘standard’ topology. A receiver employing this ‘standard’ topology would include a front sampler, a variable offset comparator, and one or more flip-flops. The front sampler is used to sample the analog value of input voltages on a pair of capacitors. The variable offset comparator then compares the sampled input voltages and decides the binary value. Then, the binary value is sent or latched to the one or more flip-flops.
Yet, the use of a front sampler does not remedy the potentially adverse effects of charge injection occurring in the sampler. Charge injection refers to the effect of a charge being capacitatively coupled or injected from a digital control line to an analog signal path as an analog switch turns on and off. Such an additional charge from a switch to a capacitor may alter the stored voltage, and ultimately lead to erroneous data detection decisions.
Furthermore, in cases where a receiver uses a half-rate clock, for example, a clock of 5 GHz (gigahertz) may be used for 10 Gb/s (gigabits per second) of data. In such a case, the incoming data needs to be sampled on both clock edges and requires two parallel receivers. Under the ‘standard’ topology, each receiver would also require its own front sampler, as a single sampler cannot handle the data for both receivers. In such situations, each sampler would also require its own digital-to-analog converter (DAC) to provide for any offset adjustments to the local receiver clock. Such an arrangement may require substantial area and power consumption of the circuit.